Latch based, non-volatile memory devices are known in the art. The basic element of such a device includes a non-volatile memory cell and a latch unit which is connected thereto. The latch unit provides an indication of the data which is stored in the cell by providing an output electrical signal.
When the memory device is initiated (such as during power-up), it is necessary to determine the time period after which the data contained therein is valid for retrieval. It is noted that during the initiation stage, the variations in the behavior of the device, due to its structure, the voltage levels provided thereto, as well as other environmental conditions, are not stable and induce considerable constraints over the process of validation of the content of the cells.
Reference is now made to FIG. 1 which is a schematic illustration of a plurality of data cells, generally referenced 10, and a reference cell, generally referenced 20, known in the art. The gate ends of data cells 10A, 10B, 10C and 10D and reference cell 20 are connected to a common line 18. Each of the data cells 10A, 10B, 10C and 10D are connected to a pair of terminal lines 12A-14A, 12B-14B, 12C-14C and 12D-14D, respectively. Reference cell 20 is connected to terminal lines 22 and 24.
Reference is further made to FIG. 2 which is a schematic illustration of a memory cell and latch device, known in the art. Latch device 50 includes two switching transistors 54 and 52, a capacitor 56, a latch formed of two inverters 60 and 62 (both powered by a power supply Vdd) and a transistor 68. The device 50 is connected to a memory cell, having a source 14, a drain 12 and a gate 18.
Inverter 60 is connected to capacitor 56, via line 58, and to the source of transistor 68, via line 64, facing the transistor 68. Inverter 62 is connected to capacitor 56, via line 58, and to the source of transistor 68, via line 64, facing the capacitor 56.
Switching transistor 52 is connected between the drain 12 of the memory cell and the ground. Switching transistor 54 is connected between source 14 of the memory cell and a line 58. Both switching transistors are activated by the same transfer signal which is provided by the system (not shown).
The capacitor 56 is further connected to the ground. The drain of the transistor 68 is also connected to the ground. The gate of the transistor 68 is connected to a voltage source (not shown) which is used to "clear" the device 50. The memory cell gate is connected to common line 18.
As the gate of the transistor 68 receives a "clear" signal, it connects line 64 to the ground, thereby decreasing the voltage level exhibited on line 64. As a result, inverter 62 inverts a low potential on line 64 to a high potential on line 58 and charges the capacitor 56. The current which is provided by inverter 62 is denoted I.sub.CHARGE.
When switching transistors 52 and 56 are activated, cell 10 is connected to the rest of the device. As the gate voltage V.sub.GATE of cell 10 rises, cell 10 conducts electrical current (I.sub.DISCHARGE) according to its programmed state, which is defined by its threshold voltage V.sub.T. A programmed cell is characterized by a high threshold voltage and, as a result, when V.sub.GATE is applied thereto, the programmed cell hardly conducts charge (I.sub.DISCHARGE &lt;&lt;I.sub.CHARGE). An erased cell, on the other hand, is characterized by a low threshold voltage which produces significant current (I.sub.DISCHARGE &gt;I.sub.CHARGE) when V.sub.GATE is applied to the cell.
An erased cell, being able to conduct large currents, discharges the capacitor 56 to the ground, thereby yielding a ground potential over line 58. At this stage, the inverter 60 inverts the low potential over line 58 to high potential over line 64.
On the other hand, a programmed cell, being able to conduct only low currents, does not conduct enough current to discharge the capacitor 56 to the ground. Accordingly, the potential over line 58 remains high. At this stage, the potential over line 58 remains high and the inverter 60 maintains a low potential over line 64. Thus, the output of device 50 remains unchanged for a programmed cell.
It is noted that the inversion time T.sub.INVERSION which an erased cell takes to invert the output of device 50, after which the data of the output signal is considered "valid", varies for different possible values of the threshold voltage V.sub.T of the cell, the profile of V.sub.GATE , the characteristics of the components of device 50, the speed at which the power supply Vdd rises and the like.
Hence, an additional mechanism is required for determining when the data at the output of the device 50 is valid for the content of such a cell. It is known in the art to use an additional cell (a reference cell) for determining the exact point in time when a conventional cell becomes valid. It is desired that the data cell become valid before the reference cell, so that the validity of the reference cell indicates the validity of the data cell.
The power up ramp rate primarily affects the speed at which the latch formed of inverters 60 and 62) initially charges capacitor 56 and the speed at which the gate voltage V.sub.GATE rises. Since cell 10 (whether as a data or a reference cell) must first overcome the voltage stored on capacitor 56 before device 50 can produce a valid signal, the power up ramp rate affects the ability of the cell to do so. For a given ramp rate, how quickly the cell can overcome the capacitor voltage is a function of the characteristics of the cell, both its charge transfer characteristics and its threshold voltage V.sub.T.
The charge transfer characteristics of a cell are determined according to the cell tunnel width (W) and the cell tunnel length (L). With a low W/L ratio, the cell transfers charge slowly. Alternatively, with a high W/L ratio, the cell transfers charge quickly. Accordingly, in the prior art, the (W/L).sub.DATA ratio of a data cell is set higher than the (W/L).sub.REFERENCE of a reference cell. As a result, the drive current of the reference cells is smaller than the drive current of the data cells and the validity time period of a reference cell is generally longer than the validity time period of a data cell. It is common to set ##EQU1##
A cell basically operates in three modes, a cut off mode, a sub-threshold mode and a saturated strong inversion mode.
When the gate voltage V.sub.GATE, provided to the cell, is significantly lower than the threshold voltage V.sub.T which characterizes the cell, the cell is in the cut-off ode. In the cut-off mode, the cell is in a state of high impedance and hence, has substantially no conductivity.
When the gate voltage V.sub.GATE, is similar to the threshold voltage V.sub.T (i.e., .vertline.V.sub.GATE -V.sub.T .vertline.&lt;0.1 volts), the cell is in the sub-threshold mode. In the sub-threshold mode, the cell is in a state of medium impedance and hence has substantially low conductivity.
When the gate voltage V.sub.GATE is higher than the threshold voltage V.sub.T, the cell is in the saturated strong inversion mode. In the saturated strong inversion mode, the cell is in a state of low impedance and hence, has substantially high conductivity. It is noted that conventionally, ##EQU2##
It is noted that both the data cell and the reference cell are provided with the same V.sub.GATE level (which varies with the power supply ramp rate) but the threshold level of the data cell V.sub.T-DATA can be different than the threshold level of the cell V.sub.T-REF, due to variations in the manufacturing process, programming states, natural decay over a long period of time, and the like.
When V.sub.T-REF is lower than V.sub.T-DATA, there is a strong probability that the reference cell will be the first to transform from the sub-threshold stage to the saturated strong inversion stage and become valid (i.e., complete the transfer of the predetermined amount of charge) before the data cell. It is noted that a reference cell with low W/L, in the saturated strong inversion mode, conducts significantly higher currents than a data cell with high W/L in the sub-threshold mode. Thus, depending on the factors described above, the reference cell might indicate that the data cell is valid when this is not the case. It will be appreciated by those skilled in the art that such a situation is totally undesirable.